Several trends exist presently in the semiconductor device fabrication industry and the electronics industry. Devices are continually getting smaller and requiring less power. A reason for these trends is that more personal devices are being fabricated which are relatively small and portable, thereby relying on a small battery as its primary supply source. For example, cellular phones, personal computing devices, and personal sound systems are devices which are in great demand in the consumer market. In addition to being smaller and more portable, personal devices are requiring more computational power and on-chip memory. In light of all these trends, there is a need in the industry to provide a memory device, which has memory and logic-functions integrated onto the same semiconductor chip.
One type of fast data storage, device that has been used consistently to address the memory portion of this demand is the high density of the standard DRAM device. High density DRAM devices have been enabled by advances in photolithography and expensive dielectric materials. However, as the cell area decreases, process margins such as alignment tolerance have become limiting factors for developing a simple cost effective high density DRAM memory cell.
Several types of DRAM memory cells are used commonly, a single capacitor memory cell and a dual capacitor memory cell. The 1T1C (one, transistor and one capacitor) memory cell type requires less silicon area than the dual capacitor type, but is less immune to noise and process variations. Additionally, the 1T1C cell requires a voltage reference for determining a stored memory state.
The dual capacitor memory cell (referred to as a 2T2C memory cell) requires more silicon area, but stores complementary signals allowing differential sampling of the stored information. The 2T2C memory cell typically is more stable than a 1T1C memory cell. As illustrated in prior art FIG. 1, a 1T1C DRAM cell 105 includes one access transistor 108 and one memory storage capacitor 110. A storage node capacitor plate (storage plate) 112 of the storage capacitor 110 is connected to a source terminal (source node) 114 of the transistor 108. The 1T1C cell 105 is read from, or written into by applying a signal via the word line WL 115 to the gate 116 of the transistor, thereby coupling the storage plate 112 of the capacitor 110 to the drain 117 of the transistor and the bit line BL 118. A ground node (ground plate) 120 of the storage capacitor 110 is connected to a common ground of the memory array. A sense amplifier (not shown) is connected to the bitline 118 and detects the voltage associated with a logic value of either 1 or 0 associated with the charge of the DRAM capacitor 110. In this manner, the memory cell data is retrieved.
A characteristic of a DRAM memory is that a read operation is destructive in some applications. The data in a memory cell is then rewritten back to the memory cell after the read operation is completed. The sense amplifier usually rewrites or restores (onto that cell) the same logical state as the bit just read from the cell. If the applied read voltage was small enough not to destroy this logical state, then the read operation was not destructive. In general, a non-destructive read requires a much larger capacitor than a destructive read and, therefore, requires a larger cell size.
As illustrated, for example, in prior art FIG. 2, a 2T2C memory cell 130 in a memory array couples to a bit line (“bitline”) 132 and an inverse of the bit line (“bitline-bar”) 134 that is common to many other memory types (for example, static random access memories). Memory cells of a memory block are formed in memory rows and memory columns. The 2T2C DRAM memory cell comprises two transistors 136 and 138 and two capacitors 140 and 142, respectively. The first transistor 136 couples between the bitline 132 and a first capacitor 140, and the second transistor 138 couples between the bitline-bar 134 and the second capacitor 142. The first and second capacitors 140 and 142 have a common ground terminal.
By contrast to the expensive DRAM process, standard logic processes are simple and very cost effective. Thus, simply adding the standard DRAM process to the simpler standard logic process would be too expensive, both in terms of development and production.
Additionally, as memory cell density increases, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing cell area. One way of increasing cell capacitance is through three-dimensional cell capacitor structures, such as trenched or stacked capacitors.
Deep trench capacitors have been implemented in prior art DRAM cells below the substrate surface in what is referred to as capacitor under the bit line (CUB) type DRAM cells. Several trench capacitor cells have had process problems, particularly where increases in cell density has pressed the access transistor alongside the trench capacitor. Attempts to use short-channel lengths for the access transistor have run up against the effects of drain-induced barrier lowering. Some of the process problems presented by these prior art approaches include: the epi process from the contact hole being barely controllable; the gate dielectric grown from the gate (rather than the channel) causing a potential reliability problem; alignment tolerances between contact holes; and word lines that are patterned before the contact process. In addition, these approaches have the tendency of decreasing process margins more than conventional processes.
Prior art capacitor over bit line (COB) type DRAM memory cells have also used various configurations of planar, trenched or stacked capacitors in the metal layers and other layers over the bit line. Generally, these implementations resort to processes requiring a number of additional masking, deposition, etching, or other production process steps. These additional process steps have a great impact on manufacturing costs and capitol equipment costs particularly where they are associated with added photolithographic equipment and more complex photo processing. Defect density inevitably increases with each additional photomasking layer and compromises yield and reliability.
Thus, conventional combinations of a standard DRAM process with the simpler standard logic process have been too expensive for the applications considered.
Also, conventional prior art COB type DRAM cells integrated into the standard logic process are generally limited to the relatively thin IMD (inter-metal dielectric) layers, by comparison to some other layers under the bit line such as the PMD layer or the substrate. This may not be a problem when planar capacitors are used in the DRAM, consuming large areas of semiconductor but when three-dimensional capacitors are to be integrated into the IMD layers, depth issues become paramount.
Accordingly, there is a need in the industry to provide a simple high density memory device, which has memory and logic functions integrated onto the same semiconductor chip, permits the use of the simpler standard logic process with a minimum of process steps, yet has the high density benefits of the DRAM structure and process formed within the thicker PMD layer.